library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Sumador_8bits is
	Generic(a : in integer := 3;
			b : in integer := 5);
    Port ( 	
			clk : in STD_LOGIC;
			in_1 : in  STD_LOGIC_VECTOR (7 downto 0);
			in_2 : in  STD_LOGIC_VECTOR (7 downto 0);
			salida : out  STD_LOGIC_VECTOR (7 downto 0));
end Sumador_8bits;


architecture Behavioral of Sumador_8bits is

	--signal aux : STD_LOGIC_VECTOR (8 downto 0);
	
begin

	process (clk)                                  
  	begin
		if clk'event and clk = '1' then
			salida <= in_1 + in_2;
		end if;
  	end process;
	
	--salida <= aux (7 downto 0);
	
end Behavioral;

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